An SRAM cell holds a bit with two inverters feeding each other. The harder they hold on to one another, the more noise they survive without flipping — and you measure that by plotting each inverter's curve against the other's: you get a butterfly, and the side of the largest square that fits inside is the static noise margin (SNM). Move the controls and watch it shrink.
The cell, transistor by transistor
M1/M2 and M3/M4 are the two inverters; M5 and M6 are the access transistors, which only conduct while the word line is active. Hover over each one to see its role.
The butterfly and the square
Opening the word line eats 39% of the margin: from 398 mV holding down to 244 mV reading. That is the read disturb.
From a margin to a memory that works
A 200 mV margin does not say much on its own: what decides is how many standard deviations fit inside it. Every cell on the chip comes out slightly different, and it only takes ONE failing to spoil the word. That is why memory people talk about 6σ rather than «enough».
This is an illustration, not an analysis. It assumes the margin follows a bell curve and that cells fail independently. Real work uses Monte-Carlo with the foundry's variability models, and the real tail is not a bell curve. Use it to understand why array size matters; not to decide anything.
All three panels use first-order models and say so in place. There is no design-rule checking here, no parasitic extraction and no automatic place and route: that is professional software and it does not fit — nor should it — in a browser tab. For real layout: Magic, OpenROAD or KLayout. And if what you want is to draw the silicon layer by layer and see it in cross-section, SiliWiz does exactly that, and does it well.